1. Technical Field
The present invention relates to a DLL (Delay Locked Loop) circuit and a method of controlling the same, and in particular, to a DLL circuit that may accurately output a clock having an improved duty ratio quality and a method of controlling the same.
2. Related Art
Generally, a DLL circuit is used to supply an internal clock having an earlier phase than a reference clock, which is obtained by converting an external clock, for a predetermined time. The internal clock is generated to allow a semiconductor memory apparatus having a relatively high integration density, such as a synchronous DRAM (SDRAM) or the like, to operate in synchronization with the external clock.
More specifically, a clock input buffer receives an external clock and outputs an internal clock. At this time, the internal clock has a phase delayed from the external clock for a predetermined time by the clock input buffer. The phase of the internal clock is additionally delayed by delay elements in the semiconductor integrated circuit, and then transmitted to a data output buffer. Subsequently, the internal clock controls the data output buffer to output data.
Accordingly, output data is delayed as compared with the external clock for a considerable amount of time. A phase of the external clock is staggered with the output data.
To solve this problem, a DLL circuit is used. The DLL circuit adjusts the phase of the internal clock to be earlier than the external clock for a predetermined time. Accordingly, output data is not delayed as compared with the external clock. That is, the DLL circuit receives the external clock and generates the internal clock having an earlier phase than the external clock for a predetermined time.
In a semiconductor memory apparatus, such as a DDR (Double Data Rate) SDRAM, a dual loop type DLL circuit is used to generate a rising clock and a falling clock. The DLL circuit includes a phase mixer that adjusts the duty ratio of a clock output from a delay line to 50%. The DLL circuit includes feedback lines each having a delay line, a delay modeling unit, and a phase comparator. Each of the delay lines performs a coarse delay operation and a fine delay operation under the control of an operation mode setting unit.
In the DLL circuit according to the related art, which includes a dual loop and controls the duty ratio of the clock using the phase mixer, a clock having a predetermined duty ratio is not accurately generated. The phase mixer has a plurality of drivers that is provided at its pull-up section, a plurality of drivers that is provided at its pull-down section, and a driving section that is provided to drive a voltage formed at a node between the pull-up section and the pull-down section. The plurality of drivers provided in the phase mixer has driving ability that may change according to a change in PVT (Process, Voltage, and Temperature). When a difference in driving ability between the drivers at the pull-up section and the pull-down section occurs due to the change in PVT, if the level of the voltage formed at the node between the pull-up section and the pull-down section is changed, the voltage on the node may be dominantly influenced by the driving ability of one of the pull-up section or the pull-down section. Accordingly, a clock having a predetermined duty ratio is not accurately generated. Further, when a low-frequency clock signal is input to the DLL circuit, a more accurate duty ratio correction operation is needed, but the DLL circuit does not perform such a duty ratio correction operation.
However, the DLL circuit according to the related art includes two feedback loops, each having a circuit for controlling the phase mixer. Thus, an area where the components are disposed is not so small. Further, in the case where the low-frequency clock signal is input to the DLL circuit, the phase mixer needs to have a considerable number of elements. Therefore, in view of the area where the components are disposed, the DLL circuit according to the related art has problems, and accordingly power consumption of the individual components becomes high. As a result, low-power consumption and high integration density of the semiconductor integrated circuit are not easily realized.